An isolated synchronous rectifying DC/DC converter is utilized for various power source circuits including an AC/DC converter.
FIG. 7 is a circuit diagram illustrating an example of a partial configuration on a secondary side of an isolated synchronous rectifying DC/DC converter. The configuration on the secondary side illustrated in FIG. 7 is common to a flyback converter and an LLC converter.
A secondary winding W200 illustrated in FIG. 7 is included in a transformer Tr. A primary side (not shown) of the isolated synchronous rectifying DC/DC converter includes a primary winding of the transformer Tr, a switching transistor, a primary side controller for driving the switching transistor, and the like.
One end of the secondary winding W200 is connected to an output terminal (not shown), and the other end thereof is connected to a drain of a synchronous rectification transistor M200. A source of the synchronous rectification transistor M200 is connected to a ground application terminal.
The isolated synchronous rectifying DC/DC converter includes a synchronous rectification controller 300S on the secondary side. The synchronous rectification controller 300S has a gate terminal G10, a drain terminal D10, a source terminal S10, and a ground terminal GND as external terminals. A gate of the synchronous rectification transistor M200 is connected to the gate terminal G10. The drain of the synchronous rectification transistor M200 is connected to the drain terminal D10. The source of the synchronous rectification transistor M200 is connected to the source terminal S10. The ground application terminal is connected to the ground terminal GND.
The synchronous rectification controller 300S outputs a gate signal GS from the gate terminal G10 based on a drain voltage VDS2 generated at the drain terminal D10 to control switching of the synchronous rectification transistor M200. By the switching of the switching transistor on the primary side and the switching of the synchronous rectification transistor M200, an input voltage applied to the primary winding is converted to an output voltage and outputted from the output terminal.
Specifically, the synchronous rectification controller 300S includes a driver Dr1, a first comparator CP1, a second comparator CP2, a flip-flop FF1, a first diode D1, and a second diode D2.
The drain terminal D10 is connected to an inverting input terminal (−) of the first comparator CP1. A first threshold voltage VthA is applied to a non-inverting input terminal (+) of the first comparator CP1. An output terminal of the first comparator CP1 is connected to a clock terminal of the flip-flop FF1. The drain terminal D10 is connected to an inverting input terminal (−) of the second comparator CP2. A second threshold voltage VthB is applied to a non-inverting input terminal (+) of the second comparator CP2. An output terminal of the second comparator CP2 is connected to a reset terminal of the flip-flop FF1. A predetermined power supply voltage is applied to a D input terminal of the flip-flop FF1. A Q output terminal of the flip-flop FF1 is connected to an input terminal of the driver Dr1. An output terminal of the driver Dr1 is connected to the gate terminal G10. A low potential side of the driver Dr1 is connected to the source terminal S10.
The first threshold voltage VthA and the second threshold voltage VthB are set based on a potential of the source terminal S10. A negative voltage is generated in the drain voltage VDS2 by the switching of the switching transistor on the primary side, and the first comparator CP1 detects that the drain voltage VDS2 becomes equal to or lower than the first threshold voltage VthA (e.g., −200 mV), and asserts an ON signal Son. Accordingly, the flip-flop FF1 sets a signal of the output terminal Q to a High level, the gate signal GS output from the driver Dr1 becomes an ON level, and the synchronous rectification transistor M200 is turned on.
When the synchronous rectification transistor M200 is turned on, a current Is starts to flow from the source to the drain of the synchronous rectification transistor M200. The drain voltage VDS2 is generated by the current Is and on-resistance of the synchronous rectification transistor M200, and the second comparator CP2 detects zero current at which the current Is becomes substantially zero based on the drain voltage VDS2. Specifically, when the second comparator CP2 detects that the drain voltage VDS2 becomes equal to or higher than the second threshold voltage VthB (e.g., −6 mV), an OFF signal Soff is asserted. Accordingly, the flip-flop FF1 is reset, the signal of the Q output terminal is set to a Low level, the gate signal GS output from the driver Dr1 becomes an OFF level, and the synchronous rectification transistor M200 is turned off.
Here, if the second threshold voltage VthB of the second comparator CP2 is set based on a ground, the detection by the second comparator CP2 is affected by parasitic impedance R1 between the ground and the source of the synchronous rectification transistor M200. Therefore, by setting the second threshold voltage VthB based on the potential of the source terminal S10, the drain voltage VDS2, which is set based on the source that is not affected by the impedance R1, can be used for detection of the second comparator CP2. Thus, it is possible to accurately detect the timing of turning off the synchronous rectification transistor M200.
In addition, the first diode D1 and the second diode D2, which are connected in parallel in opposite directions to each other, are arranged between the source terminal S10 and the ground terminal GND. Thus, when the source terminal S10 and the source of the synchronous rectification transistor M200 are opened (source open), i.e., when an abnormality occurs, assuming that a forward voltage of the first diode D1 is Vf1 and a forward voltage of the second diode D2 is Vf2, the voltage of the source terminal S10 is clamped in a voltage of not less than −Vf1 and not more than +Vf2, thereby preventing it from being unstable.
However, in the configuration illustrated in FIG. 7, when a source open occurs, there may be a case where the threshold voltage applied to the non-inverting input terminal of the second comparator CP2 becomes Vf2+VthB. For example, when Vf2 is +0.6 V and VthB is −6 mA, Vf2+VthB becomes a positive voltage which is approximately +0.6 V.
Then, the second comparator CP2 cannot assert an OFF signal Soff unless the drain voltage VDS2, which is set based on the current Is flowing when the synchronous rectification transistor M200 is turned on, is equal to or higher than a predetermined positive voltage (e.g., +0.6 V). Therefore, after the current Is flowing from the source to the drain of the synchronous rectification transistor M200 flows backward, an OFF signal Soff is asserted and the synchronous rectification transistor M200 is turned off. At this time, since the energy stored in the secondary winding W200 is applied to the synchronous rectification transistor M200, there may be a concern that an avalanche breakdown in which a large current flows through the synchronous rectification transistor M200 occurs and the synchronous rectification transistor M200 is destroyed.
Even when the source terminal S10 and the ground terminal GND are not connected by a diode, if the voltage of the source terminal S10 is unstable and becomes a positive voltage when a source open occurs, the threshold voltage applied to the non-inverting input terminal of the second comparator CP2 becomes a positive voltage, which causes the problem as described above.